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1 ? 80v, 1.25a peak current h-bridge fet driver the HIP4082 is a medium frequency, medium voltage h-bridge n-channel mosfet driver ic, available in 16 lead plastic soic (n) and dip packages. specifically targeted for pwm motor control and ups applications, bridge based designs are made simple and flexible with the HIP4082 h-bridge driver. with operation up to 80v, the device is best suited to applications of moderate power levels. similar to the hip4081, it has a flexible input protocol for driving every possible switch combination except those which would cause a shoot-through condition. the HIP4082?s reduced drive current allows smaller packaging and it has a much wider range of programmable dead times (0.1 to 4.5 s) making it ideal for switching frequencies up to 200khz. the HIP4082 does not contain an internal charge pump, but does incorporate non-latching level-shift translation control of t he upper drive circuits. this set of features and specifications is optimized for applications where size and cost are important. for applications needing higher driv e capability the hip4080a and hip4081a are recommended. features ? independently drives 4 n-channel fet in half bridge or full bridge configurations ? bootstrap supply max voltage to 95vdc ? drives 1000pf load in free air at 50c with rise and fall times of typically 15ns ? user-programmable dead time (0.1 to 4.5 s) ? dis (disable) overrides input control and refreshes bootstrap capacitor when pulled low ? input logic thresholds compatible with 5v to 15v logic levels ? shoot-through protection ? undervoltage protection ? pb-free available applications ? ups systems ? dc motor controls ? full bridge power supplies ? switching power amplifiers ? noise cancellation systems ? battery powered vehicles ? peripherals ? medium/large voice coil motors ? related literature - tb363, guidelines for handling and processing moisture sensitive surf ace mount devices (smds) pinout HIP4082 (pdip, soic) top view ordering information part number temp. range (c) package pkg. dwg. # HIP4082ib -55 to +125 16 ld soic (n) m16.15 HIP4082ibz (note) -55 to +125 16 ld soic (n) (pb-free) m16.15 HIP4082ip -55 to +125 16 ld pdip e16.3 HIP4082ipz (note) -55 to +125 16 ld pdip (pb-free) e16.3 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 bhb bhi bli ali del v ss dis ahi bho blo alo v dd ahs aho ahb bhs july 2004 HIP4082 data sheet fn3676.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright harris corporation 1995. copyright intersil americas inc. 2003, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 HIP4082 application block diagram functional block diagram 80v gnd load HIP4082 gnd 12v ahi ali bli bhi blo bhs bho alo ahs aho 3 8 2 7 4 12 5 6 turn-on delay driver 13 level shift driver ahb ahs 9 10 11 14 15 16 1 driver turn-on delay driver turn-on delay level shift aho bhb bhs bho alo blo turn-on delay undervoltage detector v dd bhi ahi dis ali v dd del bli v ss u/v u/v
3 typical application (p wm mode switching) 80v 12v 12v dis gnd gnd to optional current controller or pwm load input + - 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 bhb bhi bli ali del v ss dis ahi bho blo alo v dd ahs aho ahb bhs overcurrent latch r dis delay resistor from optional overcurrent latch r sh HIP4082
4 absolute maximum rati ngs thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v logic i/o voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ahs, bhs . . . . . -6v (transient) to 80v (25c to 150c) voltage on ahs, bhs . . . . . -6v (transient) to 70v (-55c to150c) voltage on ahb, bhb . . . . . . . . v ahs, bhs -0.3v to v ahs, bhs +v dd voltage on alo, blo . . . . . . . . . . . . . . . . . v ss -0.3v to v dd +0.3v voltage on aho, bho . . . v ahs, bhs -0.3v to v ahb, bhb +0.3v input current, del . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5ma to 0ma phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns note: all voltages are relative v ss unless otherwise specified. thermal resistance, junction-ambient ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . see curve storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating max. junction temperature . . . . . . . . . . . . . . . . . +150c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300c (for soic - lead tips only)) operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . +8.5v to +15v voltage on v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +1.0v voltage on ahb, bhb . . . . . . . v ahs, bhs +7.5v to v ahs, bhs +v dd input current, del . . . . . . . . . . . . . . . . . . . . . . . . . -4ma to -100 a caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max supply currents & under voltage protection v dd quiescent current i dd all inputs = 0v, r del = 100k 1.2 2.3 3.5 0.85 4 ma all inputs = 0v, r del = 10k 2.2 4.0 5.5 1.9 6.0 ma v dd operating current i ddo f = 50khz, no load 1.5 2.6 4.0 1.1 4.2 ma 50khz, no load, r del = 10k ? 2.5 4.0 6.4 2.1 6.6 ma ahb, bhb off quiescent current i ahbl , i bhbl ahi = bhi = 0v 0.5 1.0 1.5 0.4 1.6 ma ahb, bhb on quiescent current i ahbh , i bhbh ahi = bhi = v dd 65 145 240 40 250 a ahb, bhb operating current i ahbo , i bhbo f = 50khz, cl = 1000pf .65 1.1 1.8 .45 2.0 ma ahs, bhs leakage current i hlk v ahs = v bhs = 80v v ahb = v bhb = 96 --1.0-- a v dd rising undervoltage threshold v dduv+ 6.8 7.6 8.25 6.5 8.5 v v dd falling undervoltage threshold v dduv- 6.5 7.1 7.8 6.25 8.1 v undervoltage hysteresis uvhys 0.17 0.4 0.75 0.15 0.90 v ahb, bhb undervoltage threshold vhbuv referenced to ahs & bhs 5 6.0 7 4.5 7.5 v input pins: ali, bli, ahi, bhi, & dis low level input voltage v il full operating conditions - - 1.0 - 0.8 v high level input voltage v ih full operating conditions 2.5 - - 2.7 v input voltage hysteresis -35- - - mv low level input current i il v in = 0v, full operating conditions -145 -100 -60 -150 -50 a high level input current i ih v in = 5v, full operating conditions -1 - +1 -10 +10 a turn-on delay pin del dead time t dead r del = 100k 2.5 4.5 8.0 2.0 8.5 s r del = 10k 0.27 0.5 0.75 0.2 0.85 s gate driver output pins: alo, blo, aho, & bho low level output voltage v ol i out = 50ma 0.65 1.1 0.5 1.2 v high level output voltage v dd -v oh i out = -50ma 0.7 1.2 0.5 1.3 v HIP4082
5 peak pullup current i o +v out = 0v 1.1 1.4 2.5 0.85 2.75 a peak pulldown current i o -v out = 12v 1.0 1.3 2.3 0.75 2.5 a switching specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k, c l = 1000pf. parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max lower turn-off propagation delay (ali-alo, bli-blo) t lphl - 25 50 - 70 ns upper turn-off propagation delay (ahi-aho, bhi-bho) t hphl - 55 80 - 100 ns lower turn-on propagation delay (ali-alo, bli-blo) t lplh - 40 85 - 100 ns upper turn-on propagation delay (ahi-aho, bhi-bho) t hplh - 75 110 - 150 ns rise time t r -920-25ns fall time t f -920-25ns minimum input pulse width t pwin-on/off 50 - - 50 - ns output pulse response to 50 ns input pulse t pwout 63 80 ns disable turn-off propagation delay (dis - lower outputs) t dislow - 50 80 - 90 ns disable turn-off propagation delay (dis - upper outputs) t dishigh - 75 100 - 125 ns disable turn-on propagation delay (dis - alo & blo) t dlplh - 40 70 - 100 ns disable turn-on propagation delay (dis- aho & bho) t dhplh r del = 10k - 1.2 2 - 3 s refresh pulse width (alo & blo) t ref-pw 375 580 900 350 950 ns truth table input output ali, bli ahi, bhi vdduv vhbuv dis alo, blo aho, bho xxxx1 0 0 xx1xx 0 0 0x010 0 0 1x0x0 1 0 01000 0 1 00000 0 0 note: x signifies that input can be either a ?1? or ?0?. electrical specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k (continued) parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max HIP4082
6 HIP4082 pin descriptions pin number symbol description 1 bhb b high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. 2 bhi b high-side input. logic level input that controls bho driver (pin 16). bli (pin 3) high level input overrides bhi high level input to prevent half-bridge shoot-through, see truth t able. dis (pin 8) high level input overrides bhi high level input. the pin can be driven by signal le vels of 0v to 15v (no greater than v dd ). 3 bli b low-side input. logic level input that controls blo driver (pin 14). if bhi (pin 2) is driven high or not connected externally then bli controls both blo and bho drivers, with dead time set by delay currents at del (pin 5). dis (pin 8) high level input overrides bli high le vel input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 4 ali a low-side input. logic level input that controls alo driver (pin 13). if ahi (pin 7) is driven high or not connected externally then ali controls both alo and aho drivers, with dead time set by delay currents at del (pin 5). dis (pin 8) high level input overrides ali high le vel input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 5 del turn-on delay. connect resistor from this pin to v ss to set timing current that defines the dead time between drivers. all drivers turn-off with no adjustable delay, so the del resistor guarantees no shoot-through by delaying the turn-on of all drivers. the voltage across t he del resistor is approximately vdd -2v. 6v ss chip negative supply, generally will be ground. 7 ahi a high-side input. logic level input that controls aho driver (pin 10). ali (pin 4) high level input overrides ahi high level input to prevent half-bridge shoot-through, see truth t able. dis (pin 8) high level input overrides ahi high level input. the pin can be driven by signal le vels of 0v to 15v (no greater than v dd ). 8 dis disable input. logic level input that when taken high sets all four outputs low. dis high overrides all other inputs. when dis is taken low the outputs are controlled by the other inputs. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 9 ahb a high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. 10 aho a high-side output. connect to gate of a high-side power mosfet. 11 ahs a high-side source connection. connect to source of a high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 12 v dd positive supply to control logic and lower gate drivers. de-couple this pin to v ss (pin 6). 13 alo a low-side output. connect to gate of a low-side power mosfet. 14 blo b low-side output. connect to gate of b low-side power mosfet. 15 bhs b high-side source connection. connect to source of b high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 16 bho b high-side output. connect to gate of b high-side power mosfet. HIP4082
7 HIP4082 timing diagrams figure 1. independent mode figure 2. bistate mode figure 3. disable function dis=0 xli xhi xlo xho t lphl t hphl t hplh t lplh t r (10% - 90%) t f (10% - 90%) x = a or b, a and b halves of bridge controller are independent and uv dis=0 xli xhi = hi or not connected xlo xho and uv dis or uv xli xhi xlo xho t dlplh t dis t dhplh t ref-pw HIP4082
8 HIP4082 performance curves figure 4. i dd supply current vs temperature and v dd supply voltage figure 5. v dd supply current vs temperature and switching frequency (1000pf load) figure 6. floating (ixhb) bias current vs frequency and load figure 7. gate source/sink peak current vs bias supply voltage at 25c figure 8. gate current vs temperature, normalized to 25c figure 9. v dd -v oh vs bias voltage temperature -60 -40 -20 0 20 40 60 80 100 120 140 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 junction temperature (c) i dd supply current (ma) v dd = 16v v dd = 15v v dd = 12v v dd = 10v v dd = 8v -60 -40 -20 0 20 40 60 80 100 120 140 4 5 6 7 8 9 10 11 12 13 14 15 16 junction temperature (c) i dd supply current (ma) 200khz 100khz 50khz 10khz 0 50 100 150 200 0 1 2 3 4 5 6 7 8 frequency (khz) loaded, nl bias currents (ma) 1000pf load no load 8 9 10 11 12 13 14 15 0.5 0.75 1 1.25 1.5 1.75 bias supply voltage (v) at 25c peak gate current (a) 1.925 0.815 i src (bias ) i snk (bias) bias 2 8 15 source sink -75 -50 -25 0 25 50 75 100 125 150 0.8 0.9 1 1.1 1.2 junction temperature (c) normalized gate sink/source current (a) 8 9 10 11 12 13 14 15 0.6 1 1.4 v dd supply voltage (v) v dd -v oh (v) 1.2 0.8 -55c -40c 0c 25c 125c 150c
9 HIP4082 figure 10. v ol vs bias voltage and temperature figure 11. undervoltage trip voltages vs tempera- ture figure 12. upper lower turn-on / turn-off propaga- tion delay vs temperature figure 13. upper/lower dis(able) to turn-on/off vs temperature (c) figure 14. full bridge level-shift current vs frequency (khz) figure 15. maximum power dissipation vs ambient temperature performance curves (continued) 8 9 10 11 12 13 14 1.4 v dd supply voltage (v) v ol (v) 15 1.2 0.8 0.6 -55c -40c 0c 25c 125c 150c 1 -60 -40 -20 0 20 40 60 80 100 120 140 160 5 5.5 6 6.5 7 7.5 8 junction temperature (c) v dd , bias supply voltage (v) lower u/v reset lower u/v set upper u/v set/reset -60 -40 -20 0 20 40 60 80 100 120 140 160 20 30 40 50 60 70 80 90 100 junction temperature (c) propagation delays (ns) upper t on upper t off lower t on lower t off -60 -40 -20 0 20 40 60 80 100 120 140 160 10 100 10 4 junction temperature (c) dis to turn-on/off time (ns) 1000 dishton dishtoff dislton disloff 0 20 40 60 80 100 0.5 1 1.5 2 switching frequency (khz) level-shift current (ma) -60 -30 0 30 60 90 120 150 0 0.5 1 1.5 2 2.5 ambient temperature (c) total power dissipation (w) soic 16 pin dip quiescent bias component
10 HIP4082 figure 16. dead-time vs del resistance and bias supply (v dd ) voltage figure 17. maximum operating peak ahs/bhs voltage vs temperature performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 100 1000 10 4 dead time resistance (k ? ) dead time (ns) v dd = 12v v dd = 9v v dd = 15v 100 50 0 50 100 150 70 75 80 85 90 temperature (c) v xhs -v ss
11 HIP4082 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HIP4082 HIP4082 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 02/02

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